P-channel metal oxide semiconductor (PMOS) transistors in integrated circuits fabricated using advanced technology nodes, such as the 65 nanometer node and beyond, face a tradeoff between series resistance and control of the effective channel length. Increasing the boron dose in the p-channel source drain (PSD) implant will desirably reduce the series resistance of the PMOS transistor, but will worsen control of the effective channel length due to diffusion of the boron (overrun) into the channel during the stress memorization technique (SMT) anneal. Reducing the boron dose will increase control of the effective channel length but will worsen the series resistance. Attaining a desired value of series resistance while maintaining a desired level of effective channel length control may be problematic.